1. Field of the Invention
The present invention relates generally to a method of fabricating a semiconductor device, and more particularly to a method of forming a dielectric layer in an integrated circuit.
2. Description of the Related Art
As the integration density of semiconductor devices has been increasing, the pattern size of semiconductor devices has been decreasing. As an example, it is clear that design rules of less than 0.18 micrometers will be used for Giga DRAMs. When the minimum design rule of a memory cell array is scaled down, the aspect ratios of the structures within the cell array are increased. Such scaling-down may also increase the aspect ratio of recessed regions between the structures. The small size of the recessed regions causes them to be insufficiently filled by a filling material, such as a dielectric, which is deposited on them. As a result, a void is created as described in Silicon Processing for the VLSI Era, Vol. 11, pp. 194-199 and U.S. Pat. No. 5,494,854. The void can cause a bridge between subsequently created conductive patterns.
The dielectric layer is typically selected from a group consisting of USG (Undoped Silicate Glass), BPSG (BoroPhosphoSilicate Glass), and HDP (High Density Plasma) oxide. The use of each of these materials has its limitations. A BPSG layer can fill the recessed regions completely without void formation. However, a BPSG layer requires a high temperature (greater than about 800xc2x0 C.) reflow process immediately after depositing the BPSG layer. Such a high temperature reflow undesirably causes diffusion of impurity ions around the junction, making it difficult to fabricate highly integrated devices with short channel lengths. In addition, a BPSG layer is etched quickly in a wet chemical (it has a relatively high etch rate with respect to a wet chemical) and thereby causes a poor vertical contact hole profile. As a result, it is difficult to form a contact hole with a small size. Also, due to a poor contact hole profile, a subsequently deposited conductive layer will have poor uniformity.
Although not requiring the above-mentioned high temperature reflow process, a USG layer formed by chemical vapor deposition (CVD) does not completely fill the recessed regions. Such incomplete filling causes voids, and is not compatible with highly integrated devices.
An HDP oxide has advantages of both BPSG and USG. HDP advantageously fills recessed regions with a small thermal budget due to its low temperature process and with relatively good recessed region-filling characteristics. However, when the aspect ratio is high, it is difficult to fill up a recessed region completely. In particular, an HDP oxide is not suitable for recessed regions having an aspect ratio of 3:1 or more.
FIGS. 1A-1C are cross-sectional views of a semiconductor device, taken at selected stages of a process of forming a dielectric layer according to the prior art. FIG. 1D is a perspective view of a portion of the semiconductor device.
Referring to FIG. 1A, a device isolation layer 4 is formed to define an active region 2 and an inactive region (not designated) in and on a semiconductor substrate 1. The device isolation layer 4 is made by a shallow trench isolation technique. A gate insulating layer 6, gate electrode 8, and gate etching mask 9 are sequentially formed on the active region 2. The gate electrode 8 is formed by sequentially depositing a polysilicon layer and a silicide layer. The gate etching mask 9 is made of a silicon nitride layer to a thickness in the range of 1000 xc3x85 to 2000 xc3x85. Then, impurity ions with low concentration are implanted into the active region 2 to form a low concentration source/drain region.
Gate spacers 10 are formed on the side walls of both the gate electrode 8 and the gate etching mask 9, thereby completely forming the gate structures. The gate spacers 10 are formed by an etching process such as an etch-back process after depositing a silicon nitride layer having a thickness in the range of 300 xc3x85 to 1500 xc3x85.
As shown in FIG. 1B, silicon oxide as a dielectric layer 16 is deposited over the substrate 1.
Finally, as shown in FIGS. 1C-1D, the top surface of the inter-layer dielectric 16 is planarized by a CMP (chemical mechanical polishing) process.
However, the foregoing method of forming a dielectric layer has the drawback of also forming voids 18 within the dielectric layer 16 as shown in FIG. 1B. Accordingly, when a polysilicon layer, for example, which is used to form pad electrodes is deposited over the semiconductor device, the polysilicon layer also penetrates into the voids 18 which are exposed by the CMP process, as shown in FIGS. 1C-1D. As a result, a bridge between pad electrodes occurs. In addition, when a void occurs in a device isolation region, a bridge between gate electrodes can occur.
Therefore, there is a need for a process of depositing a void-free dielectric layer or removing a void already formed in a dielectric layer.
The present invention was made in view of the above problems. Therefore, a feature of the present invention is directed toward providing a method of forming a void-free dielectric layer in a highly integrated device.
In accordance with one aspect of the present invention, there is provided a method of forming a void free dielectric layer on a semiconductor topology having recessed regions. A first dielectric layer is deposited over the semiconductor topology. The first dielectric layer is etched to leave a part of the first dielectric layer at bottom portions of the recessed regions. A second dielectric layer is deposited over the semiconductor topology to fill up remainders of the recessed regions.
In accordance with another aspect of the present invention, there is provided a method of forming a dielectric layer in spaces between spaced apart gate lines with an insulating layer thereon, the gate lines having been formed on a semiconductor substrate. A first inter-layer dielectric layer is deposited over the semiconductor substrate to fill the spaces. The first inter-layer dielectric layer is etched to leave a part of the first inter-layer dielectric on the spaces. A second inter-layer dielectric layer is deposited over the semiconductor substrate to fill up the remainders of the spaces. Each of the first and second inter-layer dielectric layers includes material having an etch selectivity with respect to the insulating layer.
In accordance with another aspect of the present invention, there is provided a method of forming a dielectric layer. A trench is formed in a semiconductor substrate by etching. A first dielectric layer is deposited over the substrate including the trench. The first dielectric layer is etched to leave part of the first dielectric layer on a bottom of the trench. Finally, a second dielectric layer is deposited over the substrate to fill up the remainder of the trench.
In accordance with another aspect of the present invention, there is provided a method of forming a dielectric layer. A first dielectric layer is deposited over a semiconductor substrate including a recessed region. The first dielectric layer is deposited by using helium gas as a sputtering gas. The first dielectric layer is dry etched to leave a part of the first dielectric layer on a bottom of the recessed region. A second dielectric layer is deposited over the semiconductor substrate to fill up a remainder of the recessed region with the second dielectric layer.